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PHD96NQ03LT
N-channel TrenchMOS logic level FET
Rev. 06 -- 15 March 2010 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low on-state resistance Simple gate drive required due to low gate charge
1.3 Applications
DC-to-DC convertors
1.4 Quick reference data
Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 C; VGS = 5 V; see Figure 1 and 3 Tmb = 25 C; see Figure 2 Min Typ Max 25 75 115 Unit V A W drain-source voltage Tj 25 C; Tj 175 C drain current total power dissipation gate-drain charge Symbol Parameter
Dynamic characteristics QGD VGS = 5 V; ID = 50 A; VDS = 15 V; Tj = 25 C; see Figure 11 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9 VGS = 5 V; ID = 25 A; Tj = 25 C; see Figure 9 and 10 8.4 nC
Static characteristics RDSon drain-source on-state resistance 4.2 5.6 4.95 7.5 m m
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pin 1 2 3 mb Pinning information Symbol G D S D Description gate drain source mounting base; connected to drain
2 1 3
[1]
Simplified outline
mb
Graphic symbol
D
G
mbb076
S
SOT428 (DPAK)
[1] It is not possible to make connection to pin 2.
3. Ordering information
Table 3. Ordering information Package Name PHD96NQ03LT DPAK Description plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) Version SOT428 Type number
PHD96NQ03LT_6
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
2 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM EDS(AL)S Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C tp 10 s; pulsed; Tmb = 25 C VGS = 5 V; Tmb = 100 C; see Figure 1 VGS = 5 V; Tmb = 25 C; see Figure 1 and 3 tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2 Conditions Tj 25 C; Tj 175 C Tj 175 C; Tj 25 C; RGS = 20 k Min -20 -55 -55 Max 25 25 20 65 75 240 115 175 175 75 240 185 Unit V V V A A A W C C A A mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 43 A; Vsup 15 V; drain-source avalanche RGS = 50 ; tp = 0.25 ms; unclamped energy non-repetitive VGS = 10 V; Vsup 15 V; RGS = 50 ; drain-source avalanche Tj(init) = 25 C; unclamped current
IDS(AL)S
-
75
A
120 I der (%) 80
03af09
120 Pder (%) 80
03aa16
40
40
0
0 0 50 100 150 200 Tmb (C) 0 50 100 150 Tmb (C) 200
Fig 1.
Normalized continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
PHD96NQ03LT_6
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
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NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
103 ID (A) 102
03af11
Limit RDSon = VDS/ID
tp = 10 s 100 s
1 ms DC 10 10 ms 100 ms
1 1 10 VDS (V)
102
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter Conditions Min Typ Max 1.3 Unit K/W thermal resistance from see Figure 4 junction to mounting base thermal resistance from minimum footprint; mounted on a junction to ambient printed-circuit board
Rth(j-a)
-
75
-
K/W
10 Zth(j-mb) (K/W) 1 = 0.5 0.2 10-1 0.1 0.05 0.02 10-2 single pulse 10-3 10-5
tp T P
03af10
=
tp T
t
10-4
10-3
10-2
10-1
1 tp (s)
10
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
4 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 0.25 mA; VGS = 0 V; Tj = -55 C ID = 0.25 mA; VGS = 0 V; Tj = 25 C ID = 1 mA; VDS = VGS; Tj = 175 C; see Figure 8 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 8 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 8 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 25 V; VGS = 0 V; Tj = 25 C VDS = 25 V; VGS = 0 V; Tj = 175 C VGS = 15 V; VDS = 0 V; Tj = 25 C VGS = -15 V; VDS = 0 V; Tj = 25 C VGS = 5 V; ID = 25 A; Tj = 175 C; see Figure 9 and 10 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9 VGS = 5 V; ID = 25 A; Tj = 25 C; see Figure 9 and 10 Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 13 IS = 10 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 25 V; Tj = 25 C VDS = 15 V; RL = 1.2 ; VGS = 5 V; RG(ext) = 5.6 ; Tj = 25 C; ID = 12.5 A VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 12 ID = 50 A; VDS = 15 V; VGS = 5 V; Tj = 25 C; see Figure 11 26.7 8.5 8.4 2200 725 290 18 70 75 70 0.9 43 40 1.2 nC nC nC pF pF pF ns ns ns ns V ns nC Min 22 25 0.5 1 Typ 1.5 0.05 10 10 10 4.2 5.6 Max 2.3 2 1 500 100 100 13.5 4.95 7.5 Unit V V V V V A A nA nA m m m
Static characteristics
Source-drain diode
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
5 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
80 ID (A) 60 Tj = 25 C 10 V 5 V 4.5 V 4V
03af12
80 ID (A) VDS > ID x RDSon
03af14
3.5 V
60
40
3V
40
20 VGS = 2.5 V 0
20 175 C Tj = 25 C
0
0.2
0.4
0.6
0.8
1 VDS (V)
0
0
1
2
3
VGS (V)
4
Fig 5.
Output characteristics: drain current as a function of drain-source voltage; typical values
03aa36
Fig 6.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
2.5
03aa33
10-1 ID (A) 10-2
VGS(th) (V) 2 max
10-3 min 10-4 typ max
1.5
typ
1
min
10-5
0.5
10-6 0 1 2 VGS (V) 3
0 -60
0
60
120
Tj (C)
180
Fig 7.
Sub-threshold drain current as a function of gate-source voltage
Fig 8.
Gate-source threshold voltage as a function of junction temperature
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
6 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
16 R DSon (m) 12 Tj = 25 C V GS = 3.5 V
03af13
2 a 1.5
03af18
4V 8 4.5 V 5V 10 V
1
4
0.5
0
0
20
40
60
ID (A)
80
0 -60
0
60
120
Tj (C)
180
Fig 9.
Drain-source on-state resistance as a function of gate-source voltage; typical values
03af17
Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature
104
03af16
10 VGS (V) 8 ID = 50 A Tj = 25 C VDD = 15 V 6
C (pF) C iss
103 4 C oss
2
C rss
0 0 20 40 QG (nC) 60
102
10-1
1
10
VDS (V)
102
Fig 11. Gate-source voltage as a function of gate charge; typical values
Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
7 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
80 IS (A) 60 VGS = 0 V
03af15
40
20 175 C Tj = 25 C
0
0
0.3
0.6
0.9
VSD (V)
1.2
Fig 13. Source current as a function of source-drain voltage; typical values
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
8 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428
y E b2 A A1 A E1
mounting base D1 HD
D2
2 L2 1 3
L L1
b1 e e1
b
w
M
A
c
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.93 0.46 b 0.89 0.71 b1 1.1 0.9 b2 5.46 5.00 c 0.56 0.20 D1 6.22 5.98 D2 min 4.0 E 6.73 6.47 E1 min 4.45 e 2.285 e1 4.57 HD 10.4 9.6 L 2.95 2.55 L1 min 0.5 L2 0.9 0.5 w 0.2 y max 0.2
OUTLINE VERSION SOT428
REFERENCES IEC JEDEC TO-252 JEITA SC-63
EUROPEAN PROJECTION
ISSUE DATE 06-02-14 06-03-16
Fig 14. Package outline SOT428 (DPAK)
PHD96NQ03LT_6 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
9 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history Release date 20100315 Data sheet status Product data sheet Change notice Supersedes PHP96NQ03LT-05 Document ID PHD96NQ03LT_6 Modifications:
* *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product data Product data Product data Product data Product data PHP96NQ03LT-04 PHP96NQ03LT-03 PHP96NQ03LT-02 PHP96NQ03LT-01 -
PHP96NQ03LT-05 (9397 750 09666) PHP96NQ03LT-04 PHP96NQ03LT-03 PHP96NQ03LT-02 PHP96NQ03LT-01
20020605 20020220 20011023 20011008 20010716
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
10 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.3
Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
PHD96NQ03LT_6
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
11 of 13
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PHD96NQ03LT
N-channel TrenchMOS logic level FET
whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b)
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PHD96NQ03LT_6
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 -- 15 March 2010
12 of 13
NXP Semiconductors
PHD96NQ03LT
N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 March 2010 Document identifier: PHD96NQ03LT_6

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